(1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to an integration method to enhance gate activation in a complimentary metal-oxide semiconductor (CMOS) device.
(2) Description of the Prior Art
There is a continuing trend to scale down the dimensions of a semiconductor device for purposes of enhancing device speed, density, and level of integration. In order to increase the speed of a CMOS device for example, channel length or poly-silicon gate width has been decreasing aggressively. Equivalent gate oxide thickness has to correspondingly get thinner to minimize or avoid short channel effects. However, as the gate oxide gets thinner, dopant ions used to increase the conductivity of poly-silicon gate tend to penetrate through the gate and into and through the thin gate oxide layer. This penetration causes device degradation such as large threshold voltage shifts and saturated current. Further, undesirable degradation of gate oxide integrity tends to get worse with thinning gate oxide. It turns out a trade-off exists between impurity penetration and carrier depletion for engineering gate doping.
It has therefore become necessary to increase the doping level in the gate to compensate for electron depletion. A pre-doping process has been used to increase the doping level; and this procedure significantly improves the depletion for the NMOS transistor of the CMOS device. However, in the case of PMOS transistor part, pre-doping increases boron ion penetration into the p-channel through the gate oxide thereby degrading the device properties. A conventional PMOS transistor gate structure typically consists of: a gate oxide layer on a silicon substrate, a dual gate conductor of poly-silicon layer on top of gate oxide and a metal suicide layer on top of poly-silicon. During the pre-doping process, a boron-implanted poly-silicon layer is formed and when thermally annealed boron ions from this layer diffuse along grain boundaries of the poly-silicon gate into the gate oxide and through the gate oxide into the channel region of the substrate.
When BF2+ ions are used to implant the p+ gate of the transistor, followed by high temperature annealing, a significant ion penetration takes place since F atoms released in the implantation process enhance BF2+ ion diffusion. To prevent ion penetration, some solutions have been proposed in prior art such as, use of nitrided gate oxide, oxygen-doped nitride as gate dielectric, an electron depletion preventing layer under poly-silicon gate, or implanting nitrogen or silicon into the p+ poly-silicon gate.
U.S. Pat. No. 6,027,977 describes a method of fabricating a device with MIS structure which prevents boron penetration even when the gate oxide is as thin as 3 nm or less. After forming a silicon nitride film on a semiconductor substrate, oxygen is doped into the nitride film such that oxygen-rich film is next to the substrate. A gate electrode is formed on the oxygen-doped silicon nitride film and a dopant is selectively introduced into the substrate to form source/drain regions on each side of the gate structure. When poly-silicon gate is doped with boron ions, the oxygen doped silicon nitride gate acts as a barrier to boron penetration, similar to a pure nitride gate dielectric film. Because of the oxygen-rich part of the dielectric film next to the semiconductor substrate, the trap density at the interface is almost as low as that of an undoped oxide dielectric film. Such is not the case when undoped nitride is used as a gate dielectric film.
U.S. Pat. No. 6,051,460 describes a structure and method for preventing boron penetration through a thin gate oxide of a p-channel device. Silicon implanted into the poly-silicon gate electrode functions as a diffusion barrier for boron penetration through the gate oxide into the device.
U.S. Pat. No. 6,242,348 B1 a method for the formation of a boron-doped gate layer under a cobalt silicide layer to prevent boron penetration. After forming a bilayer CoSi/poly-silicon/gate-oxide gate structure, BF2+ or B+ and N2+ ions are implanted into the stack structure and thermally treated to form the cobalt silicide (CoSi2). CoSi layer in the upper part of the gate stack serves as a barrier to significantly suppress boron penetration into and through the gate oxide.
U.S. Pat. No. 6,313,020 B1 describes a semiconductor device and a method of its fabrication. An electron depletion preventing layer is formed in the bottom portion of a poly-silicon gate. An ion-implanted layer of boron ions is then formed in the upper portion of the gate-conductor to increase its conductivity. This electron depletion preventing layer serves as a barrier to suppress boron penetration into the gate oxide.